| 摘要 |
A high speed conditional synchronous one-shot circuit includes a master flip-flop for receiving an input signal and a clock signal and generating an output signal in response to the input signal and holding the output signal while the clock signal is high, the output signal going low upon the clock signal going low. A slave flip-flop has an input for receiving the output signal from the first flip-flop and a reset terminal for receiving a reset signal when the clock signal is low, a second flip-flop generating an output signal when the clock signal is high and in response to the output signal from the first flip-flop. In another embodiment, the one-shot circuit comprises a plurality of NAND gates, each gate having a plurality of inputs and an output.
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