| 摘要 |
A universal qualified clock buffer circuit for generating high-performance, low-skew local clock signals from a single-phase source clock is presented. The universal qualified clock buffer circuit independently generates a separate clock signal from the single-phase clock signal and provides for conditional signal qualification for those logic circuits which require both control signals and clock signals to regulate the flow of data. An important aspect of the universal qualified clock buffer circuit is that delays on the output signal can be independently controlled. In a CMOS implementation, the delays of both rising and falling edges of the output signal are independently controlled using different FET sizes. To control skew and edge-rate uniformity, the universal qualified clock buffer circuit is capacitively matched to the impedance load of the circuit it drives.
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