| 摘要 |
<p>A logic element for an FPGA which can be configured as any one of a random access memory, a shift register and a lookup table. The logic element includes a plurality of memory cells (790l...7904) which are interconnected such that the data output of each cell (790i) can serve as the input to the next memory cell (790i+l). Thus the logic element effectively functions as a shift register. Shift registers of arbitrary length can be created by using a lookup table address multiplexer (200) to select any memory cell (790i) output (not necessarily the last memory cell (790i) output) of the lookup table, and by chaining lookup tables of plural logic elements in series.</p> |
