| 摘要 |
A signal delay apparatus delivers synchronous signals over long and short traces. For a signal that needs to be delayed because it will be carried on a relatively short trace, passing the signal through a clocked device such as a flip flop will delay the output by a selected number of clocks. If a relatively longer trace is longer than the shorter trace by the distance a signal travels during the selected number of clock cycles, then clock signals over the respective paths will be synchronized. In a preferred embodiment, the signals are clock signals from a clock generator.
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