| 摘要 |
In a clock signal control circuit of a semiconductor device, a first clock signal is externally supplied to a first terminal of the semiconductor device in an external clock signal mode. In an external element using mode, a second clock signal is generated on said first terminal by a clocked inverter and a self-biasing resistor composed of a P-channel MOS transistor and N-channel MOS transistor, using elements externally connected between the first terminal and a second terminal of the semiconductor device. The clock signal on said second terminal in the external clock signal mode or the external element using mode is supplied to the internal circuit of the semiconductor device using a Schnmitt trigger type of logic gate. In the external clock signal mode, the clocked inverter and the self-biasing resistor are turned off such that the generation of the second clock signal is inhibited. Further, in a clock signal stop mode, the supply of the clock signal is inhibited.
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