发明名称 TLB CONTROL SYSTEM
摘要 PURPOSE:To keep constant the hit rate of address conversion of each virtual space, by providing a mapping corresponding table from logical address to real address for independent TLB(translation look aside buffer) at each virtual space. CONSTITUTION:The conversion from the logical address to the real address under the virtual storage space under present processing is made by obtaining the correspondence table 3-i of the TLB of the virtual space with a space instruction pointer 1 indicating the virtual storage space under processing from the TLB3 being correspondence tables 3-1-3-n from the logical address and real address sectioned at each virtual storage space. This is the same as the processing of a single virtual storage space, and the upper part of the logical address 2 and the logical page address of each entry of the correspondence table 3 are compared at a comparison circuit 4 and the real address is produced with the coupling between the real page address in the coincident entry and the lower part of the logical address 2.
申请公布号 JPS5782269(A) 申请公布日期 1982.05.22
申请号 JP19800159154 申请日期 1980.11.11
申请人 FUJITSU KK 发明人 KURIYAMA MASAHIRO
分类号 G06F12/10 主分类号 G06F12/10
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