发明名称 |
Clock scan design from sizzle global clock and method therefor |
摘要 |
A scan based test methodology generates conventional functional clocks (CLK1 and CLK2) and test clocks (CLKA and CLKB) from a single input clock (GCLK). The methodology allows an integrated circuit (10) designed according to it to be tested at the part's operating frequency. Also, the test methodology is compatible with known test methodologies such as level sensitive scan design ("LSSD"). The pre-existing body of test programs and equipment can be used with a circuit incorporating the invention. The single clock requirement also simplifies design.
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申请公布号 |
US5748645(A) |
申请公布日期 |
1998.05.05 |
申请号 |
US19960654981 |
申请日期 |
1996.05.29 |
申请人 |
MOTOROLA, INC. |
发明人 |
HUNTER, CRAIG C.;REININGER, RUSSELL A. |
分类号 |
G01R31/3185;(IPC1-7):G01R31/28 |
主分类号 |
G01R31/3185 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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