| 摘要 |
Disclosed herein is a semiconductor memory device having a memory cell array, a write/read circuit which writes during the test mode a plurality of identical data to the memory cell array in response to input addresses and reads the plurality of data from the memory cell array in response to the same addresses, a comparison data register which stores data identical to the plurality of data written to the memory cell array during the test mode, a decision circuit which compares the plurality of data read from the memory cell array and the data stored in the comparison data register to decide the coincidence or noncoincidence of the levels of all the data, and outputs a decision signal of a coincidence level of a noncoincidence level, and a decision result register which is reset immediately after the start of the test mode and is set to a set level in response to a decision signal of noncoincidence level and holds the state until it is reset again. <IMAGE> |
