| 摘要 |
PROBLEM TO BE SOLVED: To reduce a circuit designer's burden without cutting off a connection between a logic circuit in a clock being not the object of a test and a logic circuit in a clock being the object of the test by connecting between the logic circuits to act in different clocks through FF. SOLUTION: Logic circuits 2-4 severally act on different clock signals 5-7 (clock A-C). A scan/reset changing circuit 21 outputs scan control signals and reset signals 22-24. Namely, FF 25 acts on a clock A and a reset 22, and FF 26 acts on a clock B and a reset 23, and FF 27 acts on a clock C and a reset 24. FF 25-27 are arranged in each of logic circuits 2-4, and the logic circuits 2-4 are mutually directly connected through FF 24-27. Thus the addition of gates is unnecessary in order to cut off a connection between the logic circuits 2-4, and a circuit designer's burden can be therefore reduced. |
