| 摘要 |
An improved high speed data transfer bus with virtual memory capability is disclosed. The bus has particular applications in computer systems which employ peripheral devices. The bus allows high speed data transfer through the use of a virtual memory scheme. Moreover, the present invention minimizes the number of lines required to implement the bus. The present invention also minimizes the am ount of time a particular device is required to wait before it can access the bus and complete a data transfer. Moreover, the present invention employs control signal s that are driven both active and inactive, facilitating interfacing the bus to lo w-power CMOS technology.
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