| 摘要 |
An instruction code is stored to an instruction ROM (2) in advance and the instruction ROM (2) outputs an instruction code signal (105) corresponding to an address signal (104). A program counter (1) sequentially outputs and stores the address signal (104) in synchronization with a clock signal (101). An instruction register (5) temporarily stores and outputs the instruction code signal (105) in synchronization with the clock signal (101). A check code generating circuit (7) generates a check code signal (114) every cycle of the clock signal (101) in accordance with a signal outputted of the instruction register (5) and the address signal (104). Thereafter, a comparator (9) detects an error in operation of the instruction ROM (2) by comparing the check code signal (114) and a check data signal (106) corresponding to the instruction code and its address value. <IMAGE> |
