| 摘要 |
PURPOSE: A transform booth multiplier is provided for decreasing a delay of a sine expansion bit. CONSTITUTION: A PPG is formed of a booth encoding mux and a full adder for generating a partial product. Xn is a most signifiant bit and is inputted into PPG11 and PPG12 of the first stage. The output of the PPG12 is inputted into a 4-2 compression cell(1), and the output of the PPG11 is inputted into the remaining 4-2 compression cells(2 through 10) except for the OR and XOR gates(21, 22, 31, 32, 41 and 2) and the 4-2 compression cell(1). The output of the PPG21 positioned in the left side among the PPGs is inputted into all OR-gates and XOR gates(21, 22, 31, 32, 41, and 42) at the same time and is inputted into the remaining 4-2 compression cells except for the 4-2 compression cells.
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