| 摘要 |
<p>A data processing system contains both a scalar processor (102) and a vector processor (104). The vector processor (104) contains a plurality of functional units (108), each of which contains a plurality of parallel pipelines, each of the pipelines contains a plurality of arithmetic and logic units (ALUs) connected via a plurality of data paths, such that data can be communicated between the ALUs during the execution of a vector instruction by the vector functional unit containing the pipeline. The operation performed by each of the cascaded ALUs and the paths through which data is to be communicated between the ALUs during the execution of a vector instruction can be controlled by configuration values held in a scalar register (105) named by the vector instruction. Through the use of this technique, multiple operations upon sets of vector data may be specified in a single short vector instruction, and further, the configuration of the pipelines can be determined dynamically in response to program input.</p> |
