发明名称 |
Fast determination of carry inputs from lower order product for radix-8 odd/even multiplier array |
摘要 |
A multiplier in a floating point processor includes a circuit to determine for each bit of the multiplier operand a 3 times booth recode and a booth recode multiplier array which implements a 3 times booth recode multiplication. The multiplier includes logic to determine a fast sign extend to replace bit positions shifted in the array as well as a rounding adder to provide a rounded result while determining the final result from the booth recode multiplier. The multiplier also includes a circuit to determine a contribution to the final multiplication result from a lower order product with out forming the entire product.
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申请公布号 |
US5729485(A) |
申请公布日期 |
1998.03.17 |
申请号 |
US19950526255 |
申请日期 |
1995.09.11 |
申请人 |
DIGITAL EQUIPMENT CORPORATION |
发明人 |
WOLRICH, GILBERT M.;SANTHANAM, SRIBALAN;OLESIN, ANDREW S. |
分类号 |
G06F7/52;(IPC1-7):G06F7/52 |
主分类号 |
G06F7/52 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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