发明名称 |
Methods of forming planarized conductive interconnects for integrated circuits |
摘要 |
A conductive planarization layer, preferably a doped polysilicon layer, is used as a planarization layer for forming a conductive interconnect, such as a memory device bit line, thereon. Etching of the doped polysilicon planarization layer may be accurately controlled to form a planarized layer of controlled thickness, without requiring high temperature reflow heating of boro-phospo-silicate glass which can degrade transistor parameters. In particular, an insulating layer is formed on spaced apart source and drain regions and on the gate therebetween. A doped polysilicon layer is formed on the insulating layer. The doped polysilicon layer is planarized. A contact hole is formed in the insulating layer and in the doped polysilicon layer, to thereby expose the source or drain region. A conductive interconnect is then formed in the contact hole and on the gate.
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申请公布号 |
US5728627(A) |
申请公布日期 |
1998.03.17 |
申请号 |
US19960747783 |
申请日期 |
1996.11.14 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
NAM, IN-HO;LEE, WON-SEONG |
分类号 |
H01L21/768;(IPC1-7):H01L21/476 |
主分类号 |
H01L21/768 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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