Method for fabricating vertical walled stacked capacitors for dram cells

摘要

A method for manufacturing an array of stacked capacitors having vertical sidewalls with increased capacitance on a dynamic random access memory (DRAM) device was achieved. The invention utilizes two masking steps and self-aligning etch back steps to form a very high density array of bottom capacitor (node) electrodes for a DRAM device. The method involves depositing and planarizing a thick first polysilicon layer over a partially completed DRAM cell. A silicon oxide layer with openings aligned over the node contact openings of the pass transistors (FETs) is formed. Silicon nitride sidewall spacers are formed in the oxide openings and a thermal oxide is grown on the first polysilicon layer. After selectively removing the nitride spacers the polysilicon is etched to form the inner sidewalls for the bottom electrode. The oxide etch mask layers are removed and a second photoresist mask is used to define the outer perimeter (sidewalls) of the array of bottom electrodes. An interelectrode dielectric is formed on the bottom electrodes and a second polysilicon layer is deposited and patterned to form the top electrodes and complete the array of vertical walled stacked capacitors on the DRAM device.