| 摘要 |
A method for fabricating a transistor having a saddle fin of a local damascene structure is provided to avoid an increase of FICD(final inspection critical dimension) and loss of a polysilicon hard mask by etching a second fin mask in a manner that has etch selectivity with a lower polysilicon hard mask. A substrate(31) is prepared in which a plurality of active regions having major and minor axes by an isolation layer are defined. A hard mask pattern is formed on the substrate, opening a line type as each active region in the minor axis direction. An ARC(anti-reflective coating) is formed on the resultant structure. A fin mask of an island type is formed on the ARC, simultaneously covering the ends of the major axis of two adjacent active regions. The ARC is selectively removed to have etch selectivity with the hard mask pattern wherein plasma including F-based gas or H2 gas can be used. By using the fin mask of the island type and the hard mask pattern, the active region and the isolation layer are selectively etched to form a saddle fin.
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