发明名称 |
Method to incorporate non-volatile memory and logic components into a single sub-0.3 micron fabrication process for embedded non-volatile memory |
摘要 |
A semiconductor fabrication process allows for the fabrication of high-voltage transistors, logic transistors, and memory cells where, as required for sub-0.3 micron device geometries, the gate oxide of the logic transistors is thinner than the tunnel oxide thickness of the non-volatile memory cells without the undesirable contamination of the gate oxide of the logic transistors or contamination of the tunnel oxide of the memory cells. In one embodiment, the tunnel oxide of the memory cells is grown to a desired thickness. In a next step, a layer of doped polysilicon which will serve as the floating gate of the memory cell(s) is immediately deposited over the tunnel oxide of the memory cells, thereby protecting the tunnel oxide from contamination in subsequent masking and etching steps. The gate oxide of the logic transistors and the gate oxide of the high-voltage transistors are then grown to a desired thickness. |
申请公布号 |
US5723355(A) |
申请公布日期 |
1998.03.03 |
申请号 |
US19970785234 |
申请日期 |
1997.01.17 |
申请人 |
PROGRAMMABLE MICROELECTRONICS CORP. |
发明人 |
CHANG, SHANG-DE TED;LY, BINH |
分类号 |
H01L21/8247;H01L27/10;H01L27/105;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):H01L21/824 |
主分类号 |
H01L21/8247 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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