| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a write controller which is available in a system that operates with a comparatively high clock frequency. SOLUTION: A CPU 100 outputs a write inhibit instruction to a write signal inhibit port 13 although a state machine 15 transmits a write signal, regardless of a write protection state. The port 13 outputs a write inhibit signal to a gate 16. Then the gate 16 does not output the write signal sent from the machine 15 to a flash EEPROM 200.</p> |
