发明名称 SIMULATED RESPONSE SIGNAL OUTPUTTING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To attain address setting despite of the address of an input and output circuit to be simulated by outputting a simulated response signal when a prescribed time elapses while a response signal is not outputted from an original inputting and outputting function circuit. SOLUTION: An address which is the same as the upper and lower limit addresses of the whole address space of a system is set in an address setting circuit 10. When an input and output to which an address corresponding to an address signal ADD outputted from a CPU is allocated is present, an acknowledge signal ACK is outputted by itself for a response. On the other hand, when any input and output to which the address corresponding to the address signal ADD is allocated is not present, a simulated response signal is outputted, and the acknowledge signal ACK is outputted from an acknowledge signal monitoring circuit 15 at the time-up point of a time count circuit 16. Thus, it is possible to facilitate a counter measure to the entire address space of this system by preparing the simulated response signal output being a simulated response signal outputting circuit having only one address setting circuit.
申请公布号 JPH1040135(A) 申请公布日期 1998.02.13
申请号 JP19960189802 申请日期 1996.07.18
申请人 MITSUBISHI ELECTRIC CORP 发明人 MOMOTA AKIHIKO;MATONO MASAHARU
分类号 G06F11/30;G06F11/00;G06F13/00 主分类号 G06F11/30
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