| 摘要 |
<p>PROBLEM TO BE SOLVED: To improve the workability of a system. SOLUTION: A reset signal outputted from a gate array 13 is prevented from being inputted to the gate of a decoder 18 and on the other hand, a power source detecting signal outputted from a power source detection IC 17 is inputted to the gate of the decoder 18. Thus, when the power source detecting signal is inputted to the decoder 18 at the time of abnormality in a power supply voltage, the decoder 18 can not designate the address of a DPRAM 19 but when a reset switch 12 is depressed at the time of resetting a local CPU 11, the decoder 18 can designate the address of the DPRAM 19. As a result, when resetting the local CPU 11, a master CPU 1 can perform access to the DPRAM 19.</p> |
