| 摘要 |
<p>A disambiguation memory incorporates checking of load/store aliasing for a plurality of destination addresses into a single wide instruction operating in a very long instruction word (VLIW) processor. The disambiguation memory utilizes direct addressing and a compiler-generated check mask to check multiple destination addresses concurrently in a compact circuit size. Software-pipelined loops are used by a compiler to accelerate calculations. Several logical loop iterations are typically executed simultaneously, potentially causing a large number of address dependencies that cannot be resolved at compile-time. A particular loop operation has the same static destination address, which is known by the compiler, in all loop iterations. However, dynamic destination addresses change as successive iterations are initated. The dynamic addresses are not available at compile time. The disambiguation memory uses based addressing to access dynamic destination addresses, thereby accessing rotating regions of the disambiguation memory. Accordingly, the disambiguation memory accesses dynamic destination addresses for software pipelined loop operation in a compact disambiguation memory size. However, loop invariant loads, loads which are inherent in all loop iterations, cannot be accessed by based addressing. Accordingly, the disambiguation memory supports selection between direct addressing and based addressing operation.</p> |
