| 摘要 |
A multiprocessor circuit having interruption restriction circuits connected between an interruption line for inputting interruption signals and each of a plurality of CPUs connected in parallel with the interruption line restricts the input of interruption signals to each CPU under certain conditions. The interruption restriction circuit counts, using a counter means, the number of interruption signals received by each CPU during a specified period set at a timer. When the count for a CPU exceeds a predetermined number, the multiprocessor circuit causes an input disabling means to disable the input of interruption signals to that CPU for the specified period of time and thereby distributes interruption signals to the plurality of CPUs almost equally.
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