| 摘要 |
A start signal is given to an SP-I/O buffer through a terminal SP1, and its pulse width is controlled by an SP control circuit. A selection signal SEL is given to a selector circuit so that the data shift direction of a bidirectional shift register is switched. When the shift direction is directed to the other side, the start signal is supplied from a terminal SP2 through an SP-I/O buffer. When the shift operation is to be done from the terminal SP1 to the terminal SP2, the output of the 38th stage which precedes the final stage, namely, the 40th stage, by two stages is derived from the terminal SP2 as an input start signal for the succeeding driver, during a time period which is longer than one cycle of a clock signal CLK. According to this configuration, a cascade connection can be realized easily and surely even when a clock signal of a higher frequency is used.
|
