发明名称 |
Complementary vertical bipolar junction transistors formed in silicon-on-saphire |
摘要 |
A method is described for fabricating a complementary, vertical bipolar semiconducting structure. An N+ silicon island and a P+ silicon island separated by a first oxide layer are formed on a sapphire substrate. An NPN junction device is formed on the N+ silicon island by epitaxially growing an N-type silicon layer on the N+ silicon island. Then, a P region is created in the N-type silicon layer. An N+ region created in the P region completes the NPN junction device. Similarly, a PNP junction device is formed by epitaxially growing a P-type silicon layer on the P+ silicon island. Then, an N region is created in the P-type silicon layer. A P+ region created in the N region completes the PNP junction device.
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申请公布号 |
US5714793(A) |
申请公布日期 |
1998.02.03 |
申请号 |
US19960700894 |
申请日期 |
1996.08.21 |
申请人 |
THE UNITED STATES OF AMERICA AS REPRESENTED BY THE SECRETARY OF THE NAVY |
发明人 |
CARTAGENA, ERIC N.;WALKER, HOWARD W. |
分类号 |
H01L21/86;H01L27/12;(IPC1-7):H01L21/822 |
主分类号 |
H01L21/86 |
代理机构 |
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地址 |
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