发明名称 PREDICTIVE PICTURE GENERATING CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To provide a predictive picture generating circuit capable of reducing the use of expensive memories as small as possible and reducing a circuit scale, cost and power consumption. SOLUTION: Four memories out of five memories 31 to 35 are used for a parallel read operation and the remaining one is used for a write operation and the memory for writing operation is switched in each picture period. An output data selector 4 receives output signals from the memories 31 to 35 as input signals and selectively outputs predictive pictures p1 to p4 for vectors v1 to v4 out of the read outputs of the memories 31 to 35 . The circuit can reduce the number of memories as compared with conventional redundant circuit constitution requiring two memories for one vector signal and the reduction of the circuit scale, cost and power consumption can be reduced.</p>
申请公布号 JPH1023419(A) 申请公布日期 1998.01.23
申请号 JP19960169391 申请日期 1996.06.28
申请人 NEC CORP 发明人 OKAMURA HIROSHI
分类号 H04N19/50;H04N19/102;H04N19/103;H04N19/139;H04N19/423;H04N19/426;H04N19/51;(IPC1-7):H04N7/32 主分类号 H04N19/50
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