发明名称 Combined adder and decoder digital circuit
摘要 An address used to access on-chip memory is calculated by summing two binary numbers to obtain an N-bit address. The N-bit address is decoded into a one-out-of-2N signal to select the addressed memory location. Instead of performing these operations sequentially, the addition and decoding are done at the same time, saving time and power and enabling changes to microprocessor organization and operation that enhance performance.
申请公布号 US5710731(A) 申请公布日期 1998.01.20
申请号 US19960646194 申请日期 1996.05.07
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 CIRAULA, MICHAEL KEVIN;DHONG, SANG HOO;SILBERMAN, JOEL ABRAHAM
分类号 G06F7/57;G06F12/02;(IPC1-7):G06F7/50 主分类号 G06F7/57
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