发明名称 Weighted addition circuit
摘要 A weighted addition circuit contains a plurality of resistances, each of which is connected to a common output at one terminal and to different input voltages at the other terminal. The voltage at the common output terminal is a balance voltage of the input resistances. The common output terminal is connected to an amplifier having an odd number of stages of inverters and a feedback resistance connecting the output of the last inverter stage to the input of the first inverter stage. Grounded low pass capacitors and/or balance resistors are also be included in the amplifier to improve the stability of the circuit and prevent undesirable oscillation. Providing a circuit containing a balance voltage of the parallel-connected input resistances allows for precise weighted addition of any number of inputs while still maintaining a small and simple circuit structure.
申请公布号 US5708385(A) 申请公布日期 1998.01.13
申请号 US19960657757 申请日期 1996.05.31
申请人 YOZAN, INC.;SHARP KABUSHIKI KAISHA 发明人 SHOU, GUOLIANG;TAKTORI, SUNAO;YAMAMOTO, MAKOTO
分类号 G06G7/14;(IPC1-7):G06G7/42 主分类号 G06G7/14
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