发明名称 Delayed detection MRC diversity circuit
摘要 A delayed detection MRC diversity circuit which does not adjust synchronization in every reception branch independently having a simple circuit constitution and superior receiving characteristics. The delayed detection MRC diversity circuit is composed of a comparison circuit for selecting a reception branch with maximum RSSI, a selector, a base band circuit such as synchronous circuit and so forth for generating a regenerative clock while adjusting bit-synchronization in terms of the reception branch with the maximum RSSI, and a MRC diversity circuit section for composing using the regenerative clock.
申请公布号 AU2613097(A) 申请公布日期 1998.01.08
申请号 AU19970026130 申请日期 1997.06.19
申请人 NEC CORPORATION 发明人 KATSUYA NAGASHIMA
分类号 H04B1/02;H04B7/08;H04L7/02;H04L7/033 主分类号 H04B1/02
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