发明名称 DECODER
摘要 PROBLEM TO BE SOLVED: To satisfy a specified responsivity by resetting a pulse output means receiving only pulses input at a specified or longer intervals among output pulses of a gate circuit and outputting after delaying for a specified time based on the second decode pulse. SOLUTION: A pulse width judgment means 122 lets only pulses with wider pulse width than a specified value among input pulses 108 pass. A delay means 124 gives a delay time equal to a pulse space intervalα. From an AND gate 125, a pair pulse or a pulse having decoded a single pulse with pulse width exceeding the pulse space intervalαis output. The output pulse of a decode circuit 101 is input in a reception resting means 106 together with the output pulse of a decode circuit 121 by way of an OR gate 131. The output pulse of the decode circuit 121 is also supplied to a reset means 132 and generates a reset pulse so as to return the reception resting means 106 and a system delay time generation means 107 to each initial state.
申请公布号 JPH09329664(A) 申请公布日期 1997.12.22
申请号 JP19960145670 申请日期 1996.06.07
申请人 NEC CORP 发明人 OSHIDA NAOTO
分类号 G01S13/76;(IPC1-7):G01S13/76 主分类号 G01S13/76
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