| 摘要 |
PROBLEM TO BE SOLVED: To reduce the shunt resistance of a parasitic vertical transistor to avoid latch up by placing n<+> - or p<+> -type buried heavily doped regions at n-type or p-type wells on a principal surface of a semiconductor substrate. SOLUTION: N-type wells 2 and p<+> -type substrate contacts 9 are formed on a principal surface of a p-type semiconductor substrate 1. NchMOSFETs 4 are formed on a principal surface of the substrate 1 and PchMOSFETs 5 are formed on the surface of the n-type wells 2. N<+> type buried regions 100 are continuously or discretely formed at the bottom ends of the wells 2. N<+> type well contacts 101 are formed on part of the principal surface of the wells 2 with n<+> type regions 102 formed between the contacts 101 and regions 100. Thus it is possible to suppress the internal potential change in the wells 2 and avoid latch up. |
