发明名称 Bit error measuring apparatus
摘要 A system measures the positions of bit errors in digital recording devices and displays the physical locations of the bit errors and their distribution in such a manner that they can be grasped visually and intuitively. The system compares a data stream to be measured with a correct data stream and measures the bit errors. The apparatus includes a data stream memory which holds the correct data stream, a comparator, a counter which totals the number of bit errors, a measured bit number counter which totals the measured data stream and determines the boundaries of the logical recording blocks of the recording medium, an error number memory which holds the number of errors in each logical recording block, and an error address memory. The physical locations of bit errors are calculated on the basis of the measured and recorded bit error information for each logical block, and the bit error information is displayed on the physical form of the recording medium.
申请公布号 US5696767(A) 申请公布日期 1997.12.09
申请号 US19950524945 申请日期 1995.09.07
申请人 HEWLETT-PACKARD COMPANY 发明人 HATTORI, ATSUSHI;YATSUDA, HIDEAKI
分类号 G11B20/18;(IPC1-7):G06F11/00 主分类号 G11B20/18
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