Method for minimizing clock skew in integrated circuits and printed circuits

摘要

Clock skew is minimized in an ASIC by grid-partitioning the IC chip into a number of preferably equal sized regions. An on-chip clock or buffer unit provides a clock signal to be distributed to buffers and clocked loads also on the IC. Equal length metal interconnect traces are formed in a preferably "H"-shaped configuration such that the termini and the center of the traces overlie buffer regions that will receive the distributed clock signal. Metallization interconnect paths are dictated by placement of joiner cells. By making each metal interconnect trace equal in overall length and in layer sub-lengths (if multiple metallization layers are present), clock skew along the interconnect traces is minimized macroscopically. A series of prioritized net lists is generated, defining interconnect paths to each region. A buffer is centrally located within each region, and is surrounded by a ring containing clocked loads to be coupled to the clock signal. The ring-shape causes the clocked loads to be substantially electrically equidistant from the associated region buffer, which minimizes skew microscopically. An updated series of netlists and a clocked load preplacement batch command file are generated, defining the clocked load connections. Placement and routing of the buffers, the clocked loads and then the remainder of the ASIC is accomplished using a conventional placement and router system. The invention may also be practiced to reduce skew in designing printed circuit boards.