发明名称 SEMICONDUCTOR MEMORY DEVICE
摘要 PROBLEM TO BE SOLVED: To resolve the problem of the coupling noise in a hierarchical bit line configuration, by lessening the influence of an upper interconnection on the chip yield. SOLUTION: Left odd-numbered sense amplifiers S/A0... are connected not only to left bit line pairs BL0, L, BL0, L- ... of corresponding rows through first transfer gate pairs TG0, a, TG0, a- ... but to upper interconnection pairs ML0, ML0- of corresponding rows through second transfer gate pairs TG0, b, TG0, b- ... and these are terminated at mid points of an array SM1 and connected to right bit line pairs BL0, R, BL0, R- ... of corresponding rows through through-hole pairs HU0, HU0- . Similarly right odd-numbered sense amplifiers S/Al... are also connected to right bit line pairs BL1, R, BL1, R- ... and left bit line pairs BL1, L, BL1, L- ... of corresponding rows with the reversed traverse relation.
申请公布号 JPH09293841(A) 申请公布日期 1997.11.11
申请号 JP19960127874 申请日期 1996.04.24
申请人 TEXAS INSTR JAPAN LTD 发明人 SUKEGAWA SHUNICHI;ABE KOICHI;SAITO MASATAKA;TACHIBANA TADASHI
分类号 G11C11/401;H01L21/8242;H01L27/108 主分类号 G11C11/401
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