| 摘要 |
<p>A data timing recovery system for clock recovery based on a pulse generator circuit (106) and an injection locked oscillator (306) ILO, which extracts the clock signal at high rate and preserves the timing information during long '0' or '1' sequences. This system may also include a clock extractor circuit (102) including the ILO, a phase aligner circuit (104) and a clock killer circuit (108). Connections to and from the system are an incoming data link (110), an outgoing data link (122), an outgoing clock link (120), an enable/disable link (114) and a loss of signal data link (156). A data link (112) connected between the pulse generator circuit and the phase aligner circuit and to the clock killer circuit. A pulse link (116) connected to the ILO. A recovered clock link (118) connected between the clock extractor circuit and the phase aligner circuit.</p> |
