| 摘要 |
A process for manufacturing an integrated circuit provides for the formation of a matrix of floating-gate non-volatile memory cells having dual polysilicon levels, with the two polysilicon levels being isolated by a gate dielectric layer (4) and an interpoly dielectric layer (9) therebetween, and for the concurrent formation of one type of thick-oxide transistor (7) in peripheral zones to the matrix. The process of the invention provides for removal, during the step of defining the first-level polysilicon (5) in order to form the floating-gate structures of the memory cells, of the polysilicon (5) from the active area zone of the thick-oxide transistor (7), so that the gate oxide of the transistor (7) results from the superposition of said first (4) and second (9) dielectric layers. <IMAGE>
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