Variable delay circuit, ring oscillator, and flip-flop circuit

摘要

In a variable delay circuit for delaying an input signal by a variable delay time from a rising edge or a falling edge of the input signal to a rising edge or a falling edge of an output signal in a digital circuit, a data signal input terminal; a first signal input terminal to which a low-level signal of a logic gate is applied; n selector circuits (n=integer larger than 0) selecting either the signal at the data signal input terminal or the signal at the first signal input terminal in response to signals applied to first selector signal input terminals; and an (n+1)-input NOR circuit to which the signal at the data signal input terminal and output signals from the selector circuits are applied. In this variable delay circuit, a delay time shorter than the delay time of a single-stage buffer circuit can be controlled using only digital circuits.