| 摘要 |
<p>A priority order processing circuit for an MPEG system adapted to determine the priority order of events generated from a multiprocessor of a decoding system utilizing MPEG1 and MPEG2 schemes while controlling operations of the system. The priority order processing circuit includes a video buffer verifier writing controller (30) for generating a writing request signal when a situation exists for storing data in an external memory, a video buffer verifier reading controller (32) for generating a reading request signal when a situation exists for reading the stored data, a display controller (34) for generating a display request signal in response to recovered data received therein, a motion compensation reading controller (36) for generating a motion compensation reading request signal when a motion compensation for the stored data is requested, a motion compensation writing controller (38) for generating a motion compensation writing request signal when the motion compensation is requested, and a priority order controller (40) for determining a priority order for various request signals respectively generated from the video buffer verifier writing controller (30), video buffer verifier reading controller (32), display controller (34), motion compensation reading controller (36) and motion compensation writing controller (38) while generating a service code for executing a data processing service. <IMAGE></p> |
