| 摘要 |
PROBLEM TO BE SOLVED: To realize packet transmission which can sufficiently use the advantage of an inter-processor network constituted of a cross point buffer system- type switch. SOLUTION: Plural header registers 24-27 are provided in the transmission device 13 of a processor 1 and parcel headers stored in a parcel header queue 16 are read to the plural header registers. The header whose FIFO memory into which data is to be written is writable is selected among the headers stored in the header registers 24-27 within a range satisfying a condition that the header which is read out in the first place is preferentially selected among the headers whose FIFO memories in the inter-processor network 2 into which the packet is written become equal. Although the parcel header 96 is the header which is read in the first place, data cannot be written into a write destination FIFO memory 74. Thus, a write destination FIFO memory 72 preferentially transmits the packet of the subsequent parcel header 97, into which data can be written. |
