Current-sensing parallel to serial converter

摘要

The converter includes a number of input latch gates formed as current sources (EL/SQ1, ... EL/SQi, ... EL/SPm) which are connected with parallel inputs (Al, ... Ai, ... Am) at an input, and with a signal bus conductor (BL) at an output side. The input latch gates are activated individually through a selection arrangement (SR) pulsed with a clock signal (CLK). An evaluation unit (BW) is connected at an input with the signal bus conductor (BL) and at an output (K4) with an output latch gate (LOUT), to form a serial output signal (B). A reference input latch gate (REL/RSQ) is provided as a current source, and is activated every time simultaneously with one of the input latch gates. The reference input latch gate is connected at an output over a reference bus conductor (RBL) with a reference evaluation unit (RBW), whereby the reference bus conductor comprises always a larger signal time width than the time width of the signal bus conductor. A ready signal (RDY) is produced from the output signal of the reference evaluation unit, and an activation signal (EN) is formed in an unit (TBUF) from the ready signal and the clock signal. The activation signal is supplied as a load signal to the output latch gate.