发明名称 System and method for reducing power consumption in an electronic circuit
摘要 While a set-associative cache memory operates in a first power mode, information is stored in up to N number of ways of the cache memory, where N is an integer number and N>1. While the cache memory operates in a second power mode, the information is stored in up to M number of ways of the cache memory, where M is an integer number and 0<M<N.
申请公布号 GB9716264(D0) 申请公布日期 1997.10.08
申请号 GB19970016264 申请日期 1997.07.31
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人
分类号 G06F1/26;G06F1/32;G06F9/38;G06F12/08;G06F15/78;G11C7/00 主分类号 G06F1/26
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