| 摘要 |
The clock generator (10) generates an output (fout) of known frequency from an internally generated high frequency signal (finternal) of unknown frequency and from a low frequency input signal (fin) of known frequency. The frequency of the internal signal is determined (18) by counting the number of transitions during one period of the input signal. The output is generated based upon the determined frequency of the internal signal. A software control unit (12) calculates a divide factor for use by a programmable divider (20) based upon the period of the input signal, the count of transitions, and the desired period for the output. The internal signal is routed through the programmable divider to divide the internal signal by an amount sufficient to produce an output having a period approximately equal to the desired output period. The clock multiplier also includes a mechanism (12) for determining whether the actual frequency of the output remains within an acceptable range of frequencies and for reprogramming the programmable divider, if necessary, to reset the output frequency to within the acceptable range of frequencies.
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