Information handling device comprising a plurality of parallel processors

摘要

The system includes numerous processors (P1 - P3, P1 - P4) designed to operate in parallel. Each processor is associated with at least an addressable space (R1 - R3, R1 - R4). All the processors and addressable spaces are in communication with each other via a common communication bus (BC;BC1 - BC4). All the processors and addressable spaces are respectively connected by connection nodes (N1 - N3; N1 - N4) formed by cable circuits. Each connection node includes at least a control unit (LC,D1,D2, MUX) for: - ensuring access priority of a processor to its own addressable space and ensuring an hierarchical access priority to the addressable spaces of the other processors.