Method for hierarchic logic verification of VLSI circuits

摘要

In a method for hierarchic logic verification of VLSI circuits a hierarchic layout circuit (1234') is acquired from the physical layout of the respective VLSI circuit using an extraction program is compared to a hierarchic logic plan circuit (1234) defined by an appertaining logic plan. They are being compared such that both the layout circuit as well as the logic plan circuit are transformed independently of one another into equivalent circuits (1234'') having a respectively minimum plurality of terminals for all sub-circuits and non-isomorphic hierarchies are brought into coincidence during the circuit comparison by temporary, partial expanding. The advantage thereby achieved is that no explicit user rules with respect to the method execution are required, and that substantially less memory space and a significantly shorter processing time are required for the implementation of the method than given non-hierarchic methods.