| 摘要 |
PROBLEM TO BE SOLVED: To obtain a correct phase synchronizing state even if a duty ratio of a generated clock is varied by securing a pulse width of a phase comparison output by which a switching transistor can be stably operated. SOLUTION: An input data pulse supplied to an input terminal 24 is supplied to a phase comparison circuit 30 consisting of FF(flip-flop) circuits 25, 26, 27 and EX OR(exclusive OR) circuits 28, 29, and it is compared with generation clock CK outputted from a VCO(voltage control oscillator) 31. Then, a constant current 21 introduced by a switching transistor Q11 is integrated in a H level period of a phase comparison output of the EX OR circuit 28. On the other hand, a constant current 31 introduced by a switching transistor Q12 is integrated in a H level period of a phase comparison output of the EX OR circuit 29. The sum of these integration values is supplied to a filter 34. Consequently, as electric charges are not increased and decreased, an output voltage level of the filter 34 is not varied, and a generation clock CK of a fixed frequency is stably generated from the VCO 31. |
