| 摘要 |
A two-stage cascaded processor engine for Digital Signal Processing (DSP) utilizing parallel multi-port memories and a plurality of arithmetic units, including adders and multiplier-accumulators (MACs) is described. The engine supports a Single Instruction Multiple Data (SIMD) architecture. Conventional cascaded processors implementing an add-multiply-accumulate-add process for Short Length Transforms have significant limitations which are removed by the invention. The two stage processor uses two multiport memories. Arithmetic units (AU) in the top stage get their operands from a top multiport RAM and arithmetic units in the bottom stage get their operands from a bottom multiport RAM. AU outputs are stored back into the same stage as multiport RAM and passed either to the next stage or the output bus. The AU outputs can be both stored back into the same stages multiport RAM or passed either to the next stage or output multiplexer, or both of the previous. The system includes and input and output bus thus allowing simultaneous input and output operations. The AUs can also get upper ends from an auxiliary input buses to allow for operations on special data such as constant coefficients with elementary subroutines. The multiple two stage processors operate in an SIMD configuration, each processor receiving the same microcoded instruction from a microstore via a microinstruction bus. Various embodiments are described.
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