| 摘要 |
<p>PROBLEM TO BE SOLVED: To obtain a memory which suppresses increase in the number of circuits, the number of wirings and the load capacity and ensures a high speed operation. SOLUTION: A common data line DQY is connected via switch gates SW0, SW1 which are alternately conducted to each data line DQ0, /DQ0, DQ1, /DQ1 of the first and second banks BK0, BK1 and this common data line DQY is connected to a read amplifier DQRA and a write drive circuit DQWD. Thereby, the read amplifier DQRA and write drive circuit DQWD are used in common for the first and second banks BK0, BK1. Since the I/O line RWDn is enough to be only a short distance between the DQRA, DQWD and data input circuit DIB, data output circuit DOB, a driving load of DQRA can be eased to ensure a high speed operation.</p> |
