| 摘要 |
PROBLEM TO BE SOLVED: To shorten the etching time of a side wall layer and to prevent a etching stopper layer to be exposed to an etchant. SOLUTION: A plurality of gate electrodes 4 and 4a are formed on a semiconductor substrate 1. On the plurality of gate electrodes 4 and 4a, an etching stopper layer is formed. On the side of the plurality of gate electrode 4 and 4a, the first side wall layer 10 is formed. An inter-layer insulation film 12 which covers a plurality of gate electrodes 4 and 4a and the side wall layer 10 is formed. On the inter-layer insulation film 12 between a plurality of gate electrodes 4 and 4a, a contact hole 15 is formed. Here, by making the etching speed of the etching stopper layer slower than that of the inter-layer insulation film 12, and the etching speed of the first side wall layer 10 equal to or faster than that of the inter-layer insulation film 12, the contact hole 15 is formed on the inter-layer insulation film 12. |
