Intermetal dielectric planarization

摘要

A process is provided for implementing inter-metal dielectric ("ILD") planarization using hydrogen silsesquioxane ("HSQ") spin-on glass ("SOG") and conformal plasma enhanced tetraethyloxysilane ("PETEOS") for submicron gaps, such as vias and interconnects, having sputtered metal interconnects. The invention is particularly suitable for use in submicron CMOS and BiCMOS, processes, such as those related to the manufacture of digital signal processors, memory, logic circuits, application specific and other process that use a minimum of double-layer metallization. <IMAGE>