Phase delay correction device

摘要

The phase correction device includes an amplifier (201) for the system clock signal (SCLK) and a phase detector (202) outputting a comparison signal (DET). The comparison signal is a comparison of the phase of the system clock signal and a chip clock signal (CCLK). A shift register (203) is used to shift data according to the comparison signal. A phase delay unit (204) supplies a clock signal (CLKD) of set phase, and a domain selection control (205) supplies a domain control signal (SEL) by detecting an overrun signal (OVF) or an underrun signal (UNF) from the shift register. The domain selector (206) supplies the drive signal (DRI).